1. Field of the Invention
This invention relates to first-in first-out (FIFO) buffering of data written to a memory section of a computer system to allow zero wait state burst write operations.
2. Description of the Related Art
The personal computer industry is evolving quickly as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful computers. To meet this ever increasing demand, microprocessors, or central processing units (CPUs), are constantly being improved by increasing their speed and capabilities. These CPU's require corresponding supporting circuitry to utilize the CPU's capabilities and to maximize the speed and efficiency of the overall computer system. One example of a high performance CPU is the i486 from the Intel Corporation (Intel) which supports burst data transfers. A burst transfer is one of the fastest methods of transferring data in a computer system. The fastest burst cycles in a typical computer system with a clock frequency of 25 or 33 MHz may require only one clock cycle for consecutive data transfers, while non-burst single data cycles require a minimum of two clock cycles for every data transfer.
Burst cycles are generally provided for data transfers between the CPU and its internal and external cache memories. Cache memory was developed to bridge the gap between fast processor cycle times and slow memory access times. Cache memory is a small amount of very fast, relatively expensive, zero wait state memory that is used to store a copy of frequently accessed code and data from main memory. The external cache memory for an i486 microprocessor, for example, may include a C5 or 82495 cache controller and an array of C8 or 82490 cache memory data chips, all from Intel. The C5 cache controller is capable of supporting burst cycles between the CPU and the cache memory and utilizing burst cycles with the main memory in the computer system. Cache memory is usually implemented using static random access memories (SRAMs) which provide the speed and simplicity required to interface with the CPU. Each C8 memory chip is implemented using SRAM technology to provide the speed required to interface with the C5 cache controller. Because of their great speed, the C8 cache memories can readily handle operations, even for up to 50 MHz operation.
The main memory of a computer system is usually implemented with dynamic RAMs (DRAMs) which, when compared to SRAMs, are higher capacity, lower cost and lower power memories which run at moderate speeds. DRAMs are desirable even though they are significantly slower than SRAMs, since main memory comprises a very large amount of memory and SRAMs are appreciably more expensive than DRAMs. Main memory would be too costly if implemented with SRAMs. DRAM memory cells are basically charge storage capacitors with drive transistors, thereby making DRAMs slower than SRAMs. Due to the capacitance of DRAMs, DRAMs require more time than SRAMs to store or write data into their memory cells, and they require separate refresh circuitry to maintain the charge of each memory cell. Further, for packaging reasons DRAMs use a multiplexed addressing structure where one-half of the memory address, referred to as the row address, is provided in a first cycle and the remainder of the address, the column address, is provided in a second cycle. The use of the multiplexed addressing saves space but consumes time. Consequently, DRAMs require extra time to provide the row and column addresses, as well as extra time to store data in its internal memory cells corresponding to the address. Therefore, DRAMs require an appreciable amount of set-up and cycle time.
A popular type of DRAM is the page mode DRAM which supports page mode addressing, wherein a row address is provided to access a page in memory, and multiple column addresses are subsequently provided to read or write data within that page of memory. For purposes of this disclosure, static column DRAMs are considered functionally the same as true page mode DRAMs and any reference to page mode DRAMS will include a reference to static column DRAMs. Once the page is initialized, reads and writes to and from the page are faster than regular DRAMs. Page mode DRAMs still require, however, a significant amount of time to provide the row addresses should the required data not be on the particular page.
Page mode DRAMs provide faster data transfer between a cache controller and main memory than regular DRAMs since once a particular page is established subsequent reads and writes to that page can be completed in less time. Page mode DRAMs are, therefore, more suitable for burst cycles than regular DRAMs. Memory and supporting logic should be fast enough to handle the high speed transfer of data when interfacing with a cache controller during a burst cycle since otherwise the cache controller must provide extra wait states during the burst cycle, thereby degrading system performance. Both the page hit or column only and page miss or row and column access times of DRAMs prevent burst cycles directly with a C5 cache controller without the insertion of an appreciable number of wait states while the DRAMs are providing the row address to access a desired page.
Memory interleaving provides a partial solution to the slower cycle times of the DRAMs, since it allows the DRAMs to effectively operate at half the speed of the cache controller. The memory is partitioned into at least two banks or ways of DRAMs so that each way only has to store half the data and, consequently, only has to access every other data packet being provided on the host data bus. For example, even-addressed data may be read from or written to a first way of DRAMs, while odd-addressed data may be read from or written to a second way of DRAMs. Interleaving the DRAMs in this manner allows each DRAM way to operate at slower speeds, thereby allowing the cache controller to operate at a higher speed. Nonetheless, page mode DRAMs still require an appreciable amount of time to provide the row addresses and to initialize the DRAM into page mode. This significant amount of setup time thus reduces system performance since the system must insert wait states while the page address is being established in the DRAMs before allowing transfer of the data in a burst cycle. Thus, even with the use of page mode DRAMs and interleaving, burst cycles from current cache controllers and microprocessors are still too fast to operate without developing extra wait states and reducing potential system performance.